1. Technical Field of the Invention
The present invention relates to the domain of field-effect transistors, e.g. MOS transistors.
2. Description of Related Art
FIG. 1 represents an example of a known MOS transistor of the prior art.
The transistor 1 comprises a channel 4 separated by two diffusion regions 2, 3, a gate region 13, a spacer 5, as well as contacts 8 corresponding to the drain, source, and gate terminals. The contacts 8 are electrically connected to lines 10, 12 and vias 11.
The contacts are etched into a layer of Pre-Metallization Dielectric (PMD) material 9. When the dimensions of the transistor are relatively small, the etching of the contacts 8 must be controlled with a relatively high precision.
A contact etch stop layer 7 or CESL may be used for this purpose. The layer 7 is relatively rich in nitrogen and is more difficult to etch than the PMD 9. The etching of locations for the contacts 8 is therefore slowed when the layer 7 is reached. It is also possible to detect the end of the etching step by monitoring the amount of oxygen released.
The etch stop layer 7 may be made of silicon nitride (Si3N4) or silicon oxynitride (SiON). The PMD 9 may be of TEOS (tetraethylorthosilicate glass), BPSG (borophosphosilicate glass), or PSG (phosphosilicate glass).
The etch stop layer 7 also allows applying stress to the rest of the transistor in order to improve its performance.
The transistor 1 also comprises a layer of silicon oxide 6 for insulating the channel 4 from the gate.
The current between the drain and source terminals IDS of a MOS transistor is a function of the voltage VDS between these terminals and a saturation voltage VDSAT. The saturation voltage VDSAT is equal to the difference VGS−VT between the voltage VGS between the gate and the source and a threshold voltage VT.
The behavior of the transistor is therefore highly dependent on the value of the threshold voltage VT.
The value of the threshold voltage VT depends on various parameters, such as the gate doping, the channel doping, the temperature, the electric field strength, or various characteristics of the oxide layer 6 between the channel and the gate. These characteristics include the thickness of the oxide layer 6, and the number of positive charges accumulated in the oxide layer 6 or in the interface between the oxide layer 6 and the channel 4. These accumulated charges can vary with the temperature and/or electric field strength, creating instabilities in the value of the threshold voltage VT.
There is a need in the art to limit these instabilities in the values of the threshold voltage VT.